Multiple electronic components in ICs must be electrically isolated in order to ensure proper device functionality. Typically isolation is achieved by breaking a diffusion ‘active’ region and forming a trench in the substrate which is filled with dielectric materials, e.g., silicon oxide or silicon nitride. Devices are formed on the ‘active’ semiconductor substrate regions which are defined by isolation structures. Among isolation structures, shallow trench isolation (STI) structures are commonly used in modern IC fabrication process.
Various semiconductor device layout configurations employing a SDB and a double diffusion break (DDB) isolation schemes have been developed, as illustrated in FIG. 1A. The SDB cell layout reduces the circuit area by one contacted poly pitch (CPP) vs. DDB cell layout thus is highly desirable to achieve a high-density functional IC design on a smaller chip area. Formation of SDB isolation in high volume manufacturing, however, represents a number of technical challenges: (a) poor epitaxial (EPI) growth at the active-STI boundary; (b) poor silicide formation due to the poor EPI growth and faceting; (c) increased risk of contact to substrate shorts ‘contact punch though’ wherein the CA punches through the source/drain (S/D) region and at least partially extends into the substrate and (d) possible channel strain loss. In one instance, fully depleted silicon-on-insulator (FDSOI) and ultra-thin silicon-on-insulator (UTSOI) devices with ultra-thin Si layer are even more susceptible to the SDB challenges as compared to bulk Si devices.
FIG. 1B shows a cross-sectional view of a FDSOI device in SDB layout. Referring to FIG. 1B, a SDB isolation region 101 is formed within a center portion of a silicon-on-insulator (SOI) layer 103, a buried oxide (BOX) layer 105 and silicon (Si) substrate 107 of a HKMG FDSOI device 100 to separate the active regions 109. The SDB isolation region 101 formed underneath the dummy gate 111 prior to raised S/D 113 formation using a standard integration method results in faceted S/D profile (not shown for illustrative convenience) along the boundary of STI 101 leading to poor EPI junction growth, poor silicide formation, increased risk of contact to substrate shorts, and increased device variability for the active devices.
A need therefore exists for a methodology for providing a method to form self-aligned SDB for FDSOI devices.